1. Field of the Invention
The present invention relates to a display device for performing display of an image by inputting a digital video signal. In particular, the present invention relates to a display device having light-emitting elements. Further, the present invention relates to an electronic apparatus using the display device.
2. Description of the Related Art
A display device having a light-emitting element in each pixel and which performs display of an image by controlling light emission of the light-emitting elements is described below.
The description in this specification is made using an element (OLED element) having a structure in which an organic compound layer which emits light when an electric field is generated is sandwiched between an anode and a cathode, as a light-emitting element; however, the invention is not limited to this. Any element which emits light by applying an electric field between the anode and the cathode can be freely used.
A display device is constituted by a display and a peripheral circuit for inputting a signal to the display.
As for constitution of the display, a block diagram is shown in FIG. 36. In FIG. 36, a display 3600 is constituted by a source signal line driver circuit 3601, a gate signal line driver circuit 3602, and a pixel portion 3603. The pixel portion includes pixels disposed in matrix.
In each pixel of the pixel portion, a thin film transistor (hereinafter referred to as a TFT) is disposed. Here, a method is described in which two TFTs are disposed in each pixel and light emission of a light-emitting element of each pixel is controlled.
A configuration of the pixel portion of the display is shown in FIG. 37. In a pixel portion 3700, source signal lines S1 to Sx, gate signal lines G1 to Gy, and power supply lines V1 to Vx are disposed, and pixels of x columns (where x is a natural number) and y rows (where y is a natural number) are disposed. Each pixel 3800 has a selecting TFT 3801, a driving TFT 3802, a storage capacitor 3803, and a light-emitting element 3804.
An enlarged diagram of one pixel of the pixel portion of FIG. 37 is shown in FIG. 38. The pixel is constituted by one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one power supply line V of the power supply lines V1 to Vx, the selecting TFT 3801, the driving TFT 3802, the storage capacitor 3803, and the light-emitting element 3804.
A gate electrode of the selecting TFT 3801 is connected to the gate signal line G, and one of either a source region or a drain region of the selecting TFT 3801 is connected to the source signal line S, while the other one is connected to a gate electrode of the driving TFT 3802 and to one electrode of the storage capacitor 3803. One of either a source region or a drain region of the driving TFT 3802 is connected to the power supply line V, while the other one is connected to an anode or a cathode of the light-emitting element 3804. The other electrode of the two electrodes of the storage capacitor 3803, which is not connected to the driving TFT 3802 and the selecting TFT 3801, is connected to the power supply line V.
In this specification, the anode of the light-emitting element 3804 is referred to as a pixel electrode whereas the cathode thereof is referred to as an opposing electrode in the case where the source region or the drain region of the driving TFT 3802 is connected to the anode of the light-emitting element 3804. On the other hand, in the case where the source region or the drain region of the driving TFT 3802 is connected to the cathode of the light-emitting element 3804, the cathode of the light-emitting element 3804 is referred to as a pixel electrode whereas the anode of the light-emitting element 3804 is referred to as an opposing electrode.
Further, a potential supplied to the power supply line V is referred to as a power supply potential, and a potential supplied to the opposing electrode is referred to as an opposing potential.
The selecting TFT 3801 and the driving TFT 3802 may both be either a p-channel TFT or an n-channel TFT.
Note that the storage capacitor 3803 need not always be provided.
For example, when an n-channel TFT used as the driving TFT 3802 has an LDD region formed so as to overlap with a gate electrode through a gate insulating film, parasitic capacitance generally called as gate capacitance is formed in this overlapping region. It is also possible to actively use this parasitic capacitance as a storage capacitor for storing a voltage applied to the gate electrode of the driving TFT 3802.
Operation in displaying an image with the pixel having the above-described configuration is described below.
A signal is inputted to the gate signal line G, and the potential of the gate electrode of the selecting TFT 3801 is changed. Through the source and the drain of the selecting TFT 3801 which are thus electrically connected, a signal is inputted to the gate electrode of the driving TFT 3802 from the source signal line S. Further, the signal is stored in the storage capacitor 3803. The gate voltage of the driving TFT 3802 is changed by the signal inputted to the gate electrode of the driving TFT 3802, thereby the source and the drain thereof are electrically connected. A potential of the power supply line V is supplied to the pixel electrode of the light-emitting element 3804 through the driving TFT 3802. In this manner, the light-emitting element 3804 emits light.
A method of expressing a gray scale with pixels having such a configuration is described.
Gray scale expression methods can be roughly classified into an analog method and a digital method. Compared to the analog method, the digital method has the advantages of not being affected by variations of a TFT as much, and being suitable for multiple gray scales.
As one example of a digital gray scale expression method, a time gray scale method is known. A time gray scale driving method is a method of expressing a gray scale by controlling a period during which each pixel of a display device emits light (see Patent Document 1).
Providing that a period for displaying one image is one frame period, one frame period is divided into a plurality of subframe periods.
Lighting or non-lighting, that is, whether the light-emitting element of each pixel is made to emit light or not is performed for each subframe period. The period during which the light-emitting element emits light in one frame period is controlled, thereby a gray scale for each pixel is expressed.
This time gray scale driving method is described in detail using timing charts in FIGS. 39A and 39B. Note that an example of expressing a gray scale by using a 4-bit digital video signal is shown in FIGS. 39A and 39B. Note also that FIG. 37 and FIG. 38 are referred to as the configurations of a pixel and a pixel portion thereof. Here, by an external power source (not shown), an opposing potential can be switched over between the same level of potential as a potential (power supply potential) of each of the power supply lines V1 to Vx, and a potential such that there is a potential difference from the potential of each of the power supply lines V1 to Vx to an extent that the light-emitting element 3804 emits light.
One frame period F1 is divided into a plurality of subframe periods SF1 to SF4 in FIG. 39A.
The gate signal line G1 is selected first in the first subframe period SF1, and a digital video signal is inputted from the source signal lines S1 to Sx to the respective pixels having the selecting TFTs 3801 with gate electrodes connected to the gate signal line G1. The driving TFT 3802 of each pixel is turned on or off by the inputted digital video signal.
Here in this specification, the term “a TFT being turned on” means that the source and the drain are electrically connected to each other by a gate voltage thereof. Further, the term “a TFT being turned off” means that the source and the drain are not electrically connected to each other by the gate voltage.
At this time, the opposing potential of the light-emitting element 3804 is set to be nearly equal to the potential (power supply potential) of each of the power supply lines V1 to Vx, therefore, the light-emitting element 3804 does not emit light even in a pixel in which the driving TFT 3802 is turned on.
Here, FIG. 39B is a timing chart showing operation of inputting a digital video signal to the driving TFT 3802 of each pixel.
In FIG. 39B, periods during which a source signal line driver circuit (not shown) samples signals corresponding to the respective source signal lines are denoted by reference symbols S1 to Sx. The sampled signals are outputted at the same time to all of the source signal lines in a blanking period in the figure. The signals thus outputted are inputted to the gate electrodes of the driving TFTs 3802 in the pixels which are selected by a gate signal line.
The aforementioned operation is repeated for all of the gate signal lines G1 to Gy, and a writing period Ta1 is completed. Note that a writing period of the first subframe period SF1 is referred to as Ta1. In general, a writing period of the j-th subframe period (where j is a natural number) is referred to as Taj.
When the writing period Ta1 is complete, the opposing potential changes so as to have a potential difference from the power supply potential to an extent that the light-emitting element 3804 emits light. A display period Ts1 thus starts. Note that a display period of the first subframe period SF1 is referred to as Ts1. In general, a display period of the j-th subframe period (where j is a natural number) is referred to as Tsj. In the writing period Ts1, the light-emitting element 3804 of each pixel emits light or does not emit light in accordance with the inputted signal.
The above operation is repeated for all of the subframe periods SF1 to SF4, thereby completing one frame period F1. Here, the length of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set appropriately, and per frame period F1, a gray scale is expressed by the sum total of the display period during which the light-emitting element 3804 emits light, of the subframe period. That is, a gray scale is expressed by the sum total of the lighting time within one frame period.
A method of expressing 2n gray scales by inputting an n-bit digital video signal is described in general. At this case, for example, one frame period is divided into n subframe periods SF1 to SFn, and the ratio of the length of the display periods Ts1 to Tsn of the subframe periods SF1 to SFn is set so as to be Ts1:Ts2: . . . :Tsn−1:Tsn=20:2−1: . . . :2−(n−2):2−(n−1). Note that the lengths of the writing periods Ta1 to Tan are equal.
By calculating the sum total of a display period Ts during which light emission state is selected in the light-emitting element 3804 within one frame period, the gray scale level of the pixel in the frame period is determined. For example, providing that n is 8 and the luminance when the pixel emits light in all the display periods is 100%, a luminance of 1% can be expressed in the case where the pixel emits light in Ts8 and Ts7, and a luminance of 60% can be expressed in the case where Ts6, Ts4 and Ts1 are selected.
Note that one subframe period may be further divided into a plurality of subframe periods.
Here, it has been required that a display device consumes as little power as possible. Low power consumption has especially been required in the case where a display device is incorporated into portable information equipment or the like and used.
In that case, in the above-described display device for expressing 24 gray scales by inputting a 4-bit digital video signal, a method for reducing power consumption of the display device has been used in which only an upper one-bit signal is used to express a gray scale. (see Patent Document 2)
[Patent Document 1]
    Japanese Patent Laid-Open No. 2001-343933[Patent Document 2]    Japanese Patent Laid-Open No.Hei11-133921
A timing chart showing a driving method of a display device in a first display mode which expresses 24 gray scales is shown in FIG. 40A and a timing chart showing a driving method of a display device in a second display mode which expresses a gray scale by using only an upper one-bit signal is shown in FIG. 40B.
Since one subframe period may be provided in the second display mode, the respective frequencies of a start pulse and a clock pulse inputted to each driver circuit (a source signal line driver circuit and a gate signal line driver circuit) can be reduced, and power consumption can be reduced more than in the case where the upper one-bit gray scale is expressed in the first display mode.
In addition, in the case where the total length of time of a writing period in the first display mode is longer than the total length of time of a writing period in the second display mode, by changing a voltage between the cathode and the anode of the light-emitting element in accordance with a period of performing display, the rate of effective lighting period per frame period is increased.
However, in such a display device, an input voltage of each driver circuit is equal in the first display mode and the second display mode, therefore, further low power consumption cannot be achieved.
In addition, a conventional display device has had a problem in that when it is exposed to strong outside light, the outside light exceeds light emission of a light-emitting element and the display becomes blurred. For example, the case of a mobile phone using a conventional display device is shown in FIGS. 42A and 42B. With respect to screen display shown in FIG. 42A, the screen display is perceived as almost black when it is exposed to strong outside light as shown in FIG. 42B. A display device using liquid crystal solves this problem by using a reflective liquid crystal display device. However, in the display device using a light-emitting element, in principle, the same way of solving the problem cannot be applied. Therefore, there is a problem.